1 ? fn9229.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. isl88041 quad voltage monitor the isl88041 is a quad voltage-monitoring supervisor designed to monitor voltages 0.7v. low voltage detection circuitry protects the user 's system from low voltage conditions, resetting the system when any of the monitored power supply voltages v1mon-v4mon fall below their respective minimum voltage thresholds. the reset signal remains asserted until all of these voltages return to proper operating levels and stabilize. each rail?s vmon point is independently adjustable by using an external resistor divider. the vmon inputs will ignore transients of less than 30s on the monitored supplies, and the rst output is guaranteed to be valid down to v dd = 1v. the rst output is open-drain to allow oring of multiple signals and interfacing to a wide range of logic levels. also, the mr input allows the user to assert reset when this input is pulled low. pinout isl88041 (8 ld soic) top view features ? quad voltage monitoring ? adjustable voltage inputs monitor voltages 0.7v ? active-low rst output ? manual reset capability ? reset signal valid down to v dd = 1v ? integrated 20k ? pull-up resistor on rst ? glitch immunity on voltage monitoring inputs ? 8 ld soic pb-free plus anneal package (rohs compliant) applications ? graphics cards ? multi voltage dsps & processors ? p voltage monitoring ? embedded control systems ? intelligent instruments ? medical equipment ? network routers ? portable battery-powered equipment ? set-top boxes ? telecommunications systems gnd mr 1 2 3 4 8 7 6 5 v2mon v3mon v1mon v4mon v dd rst ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl88041ibz 88041ibz -40 to +85 8 ld soic (pb-free) m8.15 ISL88041IBZ-T 88041ibz -40 to +85 8 ld soic (tape and reel) m8.15 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 9, 2006
2 fn9229.1 march 9, 2006 functional block diagram pin descriptions isl88041 pin name function description 1v dd bias ic from nominal 2.7v to 4v. 2rst active-low open drain reset output. internal 20k ? pull-up resistor to v dd . 3mr active low open drain mr input has a 10a pull-up to v dd . 4 gnd ground. 5 v1mon adjustable first undervoltage monitor input 6 v2mon adjustable second undervoltage monitor input 7 v3mon adjustable third undervoltage monitor input 8 v4mon adjustable forth undervoltage monitor input v dd por gnd v ref v2mon pb rst v ref v1mon v ref v3mon v ref v4mon mr v ref = 635mv 30s filter 30s filter 30s filter 30s filter isl88041
3 fn9229.1 march 9, 2006 absolute maximum rati ngs thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v vmon, rst , mr . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv (hbm) operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . . +2.7v to +4v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . .-40 c to 85 c thermal resistance (typical, note 1) ja ( c/w) 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 c maximum storage temperature range . . . . . . . . . . . -65 c to 150 c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board. see tech brief tb379 f or details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 3.3v, t a = t j = -40c - 85c, unless otherwise specified symbol parameter test conditions min typ max unit bias v dd supply voltage range 2.7 4.0 v i dd v dd supply current vmon > v ref 165 1000 a v dd _lo v dd lock out v dd low to high 2.6 v v dd _lor v dd lock out reset v dd high to low 2.4 v vmon v ref adj. reset threshold voltage 619 635 651 mv v refhyst hysteresis of v ref 10 mv v ref_rng range v ref (max) - v ref (min) 1.8 mv t fil glitch filter duration vmon glitch to rst low filter 30 s reset i pd pull-down current rst = 0.5v 2 ma r pu internal pull-up resistance 20 k ? v ol output low v dd = 1v 0.05 0.1 v t rpd v th to reset asserted delay last valid input = v th to rst release 1.5 s manual reset v mr mr input voltage mr low to high threshold 0.4v dd 0.5v dd 0.6v dd v v mrhyst hysteresis of v mr 0.065 v i pu pull-up current mr = 0.5v 10 a t md mr to deassert reset out delay mr high to rst release 50 ns t mr mr to assert reset out delay mr low to rst pulling low 15 ns isl88041
4 fn9229.1 march 9, 2006 isl88041 description and operation the isl88041 is a four voltage detection ic designed to monitor multiple voltages 0.7v. this ic is suitable for microprocessors or industrial system applicatio ns providing both reset and manual reset functions. v dd lock out applying power to the isl88041 v dd activates a lock out circuit which disables the reporting function until v dd rises to ~2.6v. as v dd bias is applied the rst output is held low before v dd = 1v. if v dd falls below ~2.4v the lock out of monitoring and reporting functions is invoked. low voltage monitoring once biased to 2.7v the ic continuously monitors and reports from one to four voltages independently through external resistor dividers comparing each vmon pin voltage to a nominal internal 0.635v reference. once all vmon input voltages rise above this threshold, the rst output is immediately deasserted by being released to be pulled high via its internal 20k ? (or optional external) pull resistor to v dd indicating that all the mini mum voltage conditions have been met (see figure 4). the rst output is open-drain to allow oring of signals and interfacin g to a range of logic levels. once any vmon input falls be low its respective user-set threshold, the rst output is pulled low af ter the glitch filter delay (t fil ) as the vmon inputs are designed to reject short undervoltage transients of approximately 30s (see figure 5). the user can customize the individual rail undervoltage threshold (v trip ) by connecting individual vmon pins to an external resistor divider according to the following formula: v trip = 0.635v(r1+r2)/r2 see figure 8 for a typical application configuration. manual reset the manual-reset input (mr ) allows the user to trigger a reset by using a push-button switch or by signaling the input low. reset is asserted and deasserted immediately upon mr transitioning through mr vth , see figures 6 and 7. figure 1 is the operational timing diagram. using the isl88041eval1 the isl88041eval1 is the evaluation platform for this product and illustrates the flexibility and simplicity of monitoring four seperate voltages. the rst output can be monitored once the v dd , gnd, and appropriate 3.3v, 2.5v, 1.8v and 1.2v supply voltage inputs are properly biased as labeled. a manual reset (mr ) input is also available for evaluation. the circuit as shown in figures 10 and 11 has resistor dividers chosen to monitor for an undervoltage threshold level of 89% of the 4 nominal voltages. figure 1 illustrates the expected behavior and figures 4 through 7 illustrate the actual ic performance in the isl88041eval1. figure 1. isl88041 operational timing diagram vmon mr rst v th 1v t md t mr >t fil 5 fn9229.1 march 9, 2006 typical performance curves figure 2. v dd current vs v dd voltage figure 3. vmon threshold vs v dd voltage figure 4. vmon high to rst high figure 5. vmon low to rst low figure 6. mr high to rst high figure 7. mr low to rst low 0.5 0.4 0.3 0.2 0.1 0 v dd bias voltage (v) 0.6 v dd bias current (ma) 2.6 3.0 3.33 3.66 4.0 vmon < vmon _l2h vmon > vmon _l2h figure 2 illustrates th e idle and active bi as currents levels. 0.645 0.642 0.639 0.636 0.633 0.627 vmon threshold (v) v dd bias voltage (v) 3.3 2.6 3.9 0.630 3.7 3.5 figure 3 shows the vmon threshold shift over the bias range, demonstrating a psrr of 105db. rst = 2v/div vmon = 1v/div 1s/div rst vmon rst = 2v/div vmon = 1v/div 10s/div vmon rst t fil ~30s rst = 1v/div mr = 1v/div 1s/div mr rst mr = 1v/div rst = 1v/div 10ns/div mr rst isl88041
6 fn9229.1 march 9, 2006 figure 8. isl88041 typical application schematic figure 9. typical isl88041 application diagram figure 10. isl88041eval1 schematic figure 11. isl88041eval1 photo typical performance curves (continued) gnd mr 1 2 3 4 8 7 6 5 v1 in v2 in v3 in vmon2 vmon3 vmon1 isl88041 vmon4 v4 in v dd rst *opt ps1 ps2 ps3 ps4 high value circuit requiring accurate voltage monitoring mr rst vmon 1- 4 isl88041 gnd mr 1 2 3 4 8 7 6 5 v_3.3 v_2.5 v_1.8 vmon2 vmon3 vmon1 isl88041 vmon4 v_1.2 v dd rst 0.1f 10k 10k 10k 10k 36.5k 24.9k 15.4k 6.98k isl88041
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9229.1 march 9, 2006 isl88041 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
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